ASIC design

*Master  - IP component that initiates a data transfer (read/ write) ex) processor , DMA (it may vary depending on the situation and point of view) *Slave - IP component  that does not initiate transfers and only responds to incoming transfer requests ex) Memory *Arbiter  - Determines which master to grant access to bus *Decoder - Determines which slave a transfer intended for *Bridge - Connects two buses 

Make a new .tcl file by copying the script below After that, source the new .tcl files in pt session. ------------------------------------------------------------------------------------------   #!/bin/csh ############################## #copyright  asic-eng.blogspot.com # Use this script in PT session. (source it) ############################## report_timing -max_paths 99999 -slack_lesser_than -0.24 > 1.rpt sh awk '/^  *ISO/' ./1.rpt >> 2.rpt sh awk '/Y */' ./2.rpt >>3.rpt sh sed '/CK/d' ./3.rpt >> 4.rpt sh sed '/D0  /d' ./4.rpt >> 5.rpt sh sed '/D1  /d' ./5.rpt >> 6.rpt sh sed '/D2  /d' ./6.rpt >> 7.rpt sh sed '/D3  /d' ./7.rpt >> 8.rpt sh sed '/QN0  /d' ./8.rpt >> 9.rpt sh sed '/QN1 /d' ./9.rpt >> 10.rpt sh sed '/QN2  /d' ./10.rpt >> 11.rpt sh sed '/TSL_/d' ./11.rpt >> 12.rpt sh sed 's/).*//g' ./12.rpt >&g

linux command diff 활용 reference와 나의 script 비교 가능 ref.txt my.txt $ > diff ref.txt my.txt > difference.txt 디렉토리의 하위 script 들 간의 비교 가능 directory -> rtl_ref (rtl1.v rtl2.v rtl3.v) directory -> rtl_my (rtl1.v rtl2.v rtl3.v)  $ > diff rtl_ref rtl_my > diff.txt

 Verilog 4-value logic system ( cf. VHDL : 9 value system ) Z is called as "Weak high"  it means, Another signal connected to it can change the value like a 0 will pull it low, a 1 will pull it high. 

Cell delay -Cell delay is the amount of delay from input to output of a logic gate in a path. -Dimensional table of delay values dependent on input net transition and output capacitance [Example] Net delay -Net delay is the amount of delay from the output of a cell to the input of the next cell in a timing path. [Methods of calculating net delay] 1)  Estimating delays WLM (In fact, these days we use the zero wire load model.->Setting the worst case using a clock derating) 2)  Using specific tiem values back-annotated from Standard Delay Format(SDF) file. 3)   RC extraction -> SPEF(Standard Parasitic Exchange Format) file.

Object class Description Command to create object collection cell Instance in the design; can be a hierarchical block or primitive library cells get_cells clock Clock get_clocks design Design get_designs lib Library get_libs lib_cell Cell in a logic library get_lib_cells lib_pin Pin on a library cell get_lib_pins lib_timing_arc Timing arc on a library cell get_lib_timing_arcs net Net in the current design get_nets path_group Group of paths for cost-function calculations and timing reports get_path_groups pin Pin of a lower-level cell in the design; can be input, output, or inout(bidirectional) get_pins port Port of the current des

1. USE Design Compiler dc_shell> list_attributes -application -class cell dc_shell> sizeof_collection [get_cells -hierarchical -filter "is_sequential==true"] 2. USE the RTL (FSD= D scan flip flop) in rtl file(.v) :%!grep -c FSD 3. list attribute -application is_sequential get_cell -hierarchical -filter "is_sequential = true'