Cell delay / Net delay
- Cell delay
-Cell delay is the amount of delay from input
to output of a logic gate in a path.
-Dimensional table of delay values dependent on input net transition and output capacitance
[Example]
- Net delay
-Net delay is the amount of delay from
the output of a cell to the input of the next cell in a timing path.
[Methods of calculating net delay]
1) Estimating delays WLM (In fact, these days we use the zero wire load
model.->Setting the worst case using a clock derating)
2) Using specific tiem values back-annotated from Standard Delay
Format(SDF) file.
3) RC extraction -> SPEF(Standard Parasitic Exchange Format) file.
- Net delay
-Net delay is the amount of delay from
the output of a cell to the input of the next cell in a timing path.
[Methods of calculating net delay]
1) Estimating delays WLM (In fact, these days we use the zero wire load
model.->Setting the worst case using a clock derating)
2) Using specific tiem values back-annotated from Standard Delay
Format(SDF) file.
3) RC extraction -> SPEF(Standard Parasitic Exchange Format) file.
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