Design objects




Object class

Description

Command to create object collection

cell

Instance in the design; can be a hierarchical block or primitive library cells

get_cells

clock

Clock

get_clocks

design

Design

get_designs

lib

Library

get_libs

lib_cell

Cell in a logic library

get_lib_cells

lib_pin

Pin on a library cell

get_lib_pins

lib_timing_arc

Timing arc on a library cell

get_lib_timing_arcs

net

Net in the current design

get_nets

path_group

Group of paths for cost-function calculations and timing reports

get_path_groups

pin

Pin of a lower-level cell in the design; can be input, output, or inout(bidirectional)

get_pins

port

Port of the current design; can be input, output, or inout (bidirectional)

get_ports

timing_arc

Timing arc

get_timing_arcs

timing_path

Timing path

get_timing_paths


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PVT

Cell delay / Net delay

Types of Vth