Verilog 4-value logic system

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 Verilog 4-value logic system ( cf. VHDL : 9 value system )


Z is called as "Weak high" 

it means, Another signal connected to it can change the value like a 0 will pull it low, a 1 will pull it high. 

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PVT

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 What is PVT? PVT stands for process, voltage, temperature. Process -Speed of nMOS/pMOS is different due to the cause of the process. -Types of speed -> fast / typical / slow -FF/FS/TT/SF/SS(nMOS/pMOS) Voltage -Speed of pMOS/nMOS changes according to the supply voltage. -In general, ±10% of the typical is taken as the best/worst case.  Temperature -Speed of pMOS/nMOS changes according to temperature -in reality, temperature inversion arises in 65nm, mostly 28nm and below. Why do we use PVT? To verify in advance timing according to process or environmental conditions. PVT corners and its effect on delay Additionally.. Synthesis 를 진행할 때의 PVT best/worst  조건은 어떤 기준에 의해서 정해 질까? Synthesis 는 아직 net 이 없는 상태 이므로 , 이후 real net 이 생긴다면 net delay 에 의해 holdtime 은 개선될 것이다 . 그러므로   synthesis 를 진행하는 경우의 PVT 에서는 setuptime 을 우선적으로 고려해 delay 의 best/worst 조건을 생각해야 한다 .  이처럼 Synthesis에서의 PVT best/worst 조건은 delay(timing)을 기준으로 한다. 구체적으로, 위의 표에서와 같이 delay를 maximum으로 하는 SS/Low voltage/High Temperature를 w
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Cell delay / Net delay

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Cell delay -Cell delay is the amount of delay from input to output of a logic gate in a path. -Dimensional table of delay values dependent on input net transition and output capacitance [Example] Net delay -Net delay is the amount of delay from the output of a cell to the input of the next cell in a timing path. [Methods of calculating net delay] 1)  Estimating delays WLM (In fact, these days we use the zero wire load model.->Setting the worst case using a clock derating) 2)  Using specific tiem values back-annotated from Standard Delay Format(SDF) file. 3)   RC extraction -> SPEF(Standard Parasitic Exchange Format) file.
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[Scan] Scan chain / Scan operation

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What is a Scan chain?  The scan cells(F/F with mux) are linked together into “scan chains” that operate like big shift registers when the circuit is put into test mode. Scan chains are used to detect manufacturing defects present in the combinational logic of the design. [Scan chain =  controllability +  observability] scan flops initialize nodes within the design(controllability) scan flops capture results from within the design(observability) inserting a scan path involves replacing all f/f with their scannable equivalent f/f larger area than non-scan registers, larger setup time requirement. Scan operation
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