Vth swap in PrimeTime

작성자:

Make a new .tcl file by copying the script below

After that, source the new .tcl files in pt session.

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 #!/bin/csh


##############################
#copyright  asic-eng.blogspot.com
# Use this script in PT session. (source it)
##############################

report_timing -max_paths 99999 -slack_lesser_than -0.24 > 1.rpt

sh awk '/^  *ISO/' ./1.rpt >> 2.rpt
sh awk '/Y */' ./2.rpt >>3.rpt
sh sed '/CK/d' ./3.rpt >> 4.rpt
sh sed '/D0  /d' ./4.rpt >> 5.rpt
sh sed '/D1  /d' ./5.rpt >> 6.rpt
sh sed '/D2  /d' ./6.rpt >> 7.rpt
sh sed '/D3  /d' ./7.rpt >> 8.rpt
sh sed '/QN0  /d' ./8.rpt >> 9.rpt
sh sed '/QN1 /d' ./9.rpt >> 10.rpt
sh sed '/QN2  /d' ./10.rpt >> 11.rpt
sh sed '/TSL_/d' ./11.rpt >> 12.rpt
sh sed 's/).*//g' ./12.rpt >> 13.rpt
sh sed 's/TL_/TSL_/g' ./13.rpt >> 14.rpt
sh sed 's/TR_/TSL_/g' ./14.rpt >> 15.rpt
sh sed 's%/Y *(% %g' ./15.rpt >> 16.rpt
sh sed s/^/size_cell/g ./16.rpt > slvt_swap.rcl

sh cat pre_eco.tcl slvt_swap.tcl > buffer.tcl
sh cat buffer.tcl >> pre_eco.tcl

sh rm -rf  1.rpt 2.rpt 3.rpt 4.rpt 5.rpt 6.rpt 7.rpt 8.rpt 9.rpt 10.rpt 11.rpt 12.rpt 13.rpt 14.rpt 15.rpt 16.rpt

source ./slvt_swap.tcl

update_timing

report_timing -max_paths 1 >> result_slvt_swap

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##Check the naming rules in timing report....


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PVT

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이미지
 What is PVT? PVT stands for process, voltage, temperature. Process -Speed of nMOS/pMOS is different due to the cause of the process. -Types of speed -> fast / typical / slow -FF/FS/TT/SF/SS(nMOS/pMOS) Voltage -Speed of pMOS/nMOS changes according to the supply voltage. -In general, ±10% of the typical is taken as the best/worst case.  Temperature -Speed of pMOS/nMOS changes according to temperature -in reality, temperature inversion arises in 65nm, mostly 28nm and below. Why do we use PVT? To verify in advance timing according to process or environmental conditions. PVT corners and its effect on delay Additionally.. Synthesis 를 진행할 때의 PVT best/worst  조건은 어떤 기준에 의해서 정해 질까? Synthesis 는 아직 net 이 없는 상태 이므로 , 이후 real net 이 생긴다면 net delay 에 의해 holdtime 은 개선될 것이다 . 그러므로   synthesis 를 진행하는 경우의 PVT 에서는 setuptime 을 우선적으로 고려해 delay 의 best/worst 조건을 생각해야 한다 .  이처럼 Synthesis에서의 PVT best/worst 조건은 delay(timing)을 기준으로 한다. 구체적으로, 위의 표에서와 같이 delay를 maximum으로 하는 SS/Low voltage/High Temperature를 w
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Cell delay / Net delay

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이미지
Cell delay -Cell delay is the amount of delay from input to output of a logic gate in a path. -Dimensional table of delay values dependent on input net transition and output capacitance [Example] Net delay -Net delay is the amount of delay from the output of a cell to the input of the next cell in a timing path. [Methods of calculating net delay] 1)  Estimating delays WLM (In fact, these days we use the zero wire load model.->Setting the worst case using a clock derating) 2)  Using specific tiem values back-annotated from Standard Delay Format(SDF) file. 3)   RC extraction -> SPEF(Standard Parasitic Exchange Format) file.
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Types of Vth

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  Types of Vth and characteristics ▪  HVT(High Threshold Voltage)     -> Low leakage current / worse timing /  used for power critical functions ▪  RVT(Regular Threshold Voltage) or SVT(Standard  Threshold Voltage) ▪  LVT(Low Threshold Voltage) ▪  sLVT(Super Low Threshold Voltage) ->Better timing / increase leakage current /  used in timing critical functions
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